Computer Architecture

Historical Perspectives with References. For each chapter in the text, there is a section devoted to a historical perspective, together with references.

References Appendices.  These appendices are available in PDF and include:

• Appendix D: Storage Systems

• Appendix E: Embedded Systems by Thomas M. Conte

• Appendix F: Interconnection Networks updated by Timothy M. Pinkston and José Duato

• Appendix G: Vector Processors by Krste Asanovic

• Appendix H: Hardware and Software for VLIW and EPIC

• Appendix I: Large-Scale Multiprocessors and Scientific Applications

• Appendix J: Computer Arithmetic by David Goldberg

• Appendix K: Survey of Instruction Set Architectures

• Appendix L: Advanced Concepts on Address Translation

• Appendix M:  Historical Perspectives and References

Lecture Slides. Lecture slides in PowerPoint (PPT) format are provided. These slides, developed by Jason Bakos of the University of South Carolina, are designed to follow the progression of topics found in the printed text, covering the key learning points of each section in Chapters 1-7.

Figures from the Text. They are provided in PowerPoint (PPT) format. These slides represents figures from the Book,

• Appendix A: Instruction Set Principles

• Appendix B: Review of Memory Hierarchy

• Appendix C: Pipelining: Basic and Intermediate Concepts

• Appendix D: Storage Systems

• Appendix E: Embedded Systems

• Appendix F: Interconnection Networks

• Appendix G: Vector Processors in More Depth

• Appendix H: Hardware and Software for VLIW and EPIC

• Appendix I: Large-Scale Multiprocessors and Scientific Applications

• Appendix J: Computer Arithmetic

• Appendix K: Survey of Instruction Set Architectures

• Appendix M: Historical Perspectives and References

• Chapter 1: Fundamentals of Quantitative Design and Analysis

• Chapter 2: Memory Hierarchy Design

• Chapter 3: Instruction-Level Parallelism and Its Exploitation

• Chapter 4: Data-Level Parallelism in Vector, SIMD, and GPU Architectures

• Chapter 5: Thread-Level Parallelism

• Chapter 6: Warehouse-Scale Computers to Exploit Request-Level and Data-Level

• Chapter 7: Domain-Specific Architectures

Errata (updated 28 Nov 2017)